A research team at The Hong Kong Polytechnic University (PolyU) has engineered a novel tunnelling field-effect transistor (TFET) using 2D nanomaterials, potentially overcoming a fundamental physical barrier that has limited the energy efficiency of conventional transistors. This breakthrough could enable ultra-low-power, high-performance integrated circuits essential for next-generation AI chips and advanced semiconductor applications.
Conventional transistors rely on thermionic emission of electrical charges, which requires a minimum gating voltage of 60 millivolts (mV). However, the 'Boltzmann limit' makes subthreshold swing (SS) values below 60 mV per decade physically impossible at room temperature, restricting progress in high-performance electronics. The PolyU-led team has broken through this boundary by adopting quantum tunnelling, a mechanism that allows charge carriers to pass through energy barriers rather than over them.
Led by Prof. Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, the research was conducted in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The findings have been published in the prestigious scientific journal Science.
Prof. Hao explained, 'By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.'
The team created an ultra-thin heterostructure of alternating 2D bismuth and indium selenide layers using pulsed laser deposition. By precisely controlling the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in 2D form, allowing charge carriers to tunnel efficiently into indium selenide through quantum tunnelling. The resulting TFET achieved SS values well below the 60 mV per decade limit. Operating at room temperature on silicon substrates, the device required a gate-voltage range of only 160 mV—far lower than the 800 mV originally required.
The device also resolved a challenge in experimental TFETs by delivering a high output current alongside an exceptionally high ON/OFF current ratio, which is critical for driving multiple downstream logic gates and diminishing circuit delay. This combination of low power consumption and high performance is crucial for the continued scaling of microelectronics, especially as the industry approaches the physical limits of conventional transistors.
This development is significant because it offers a viable path to overcome the Boltzmann limit, a major obstacle in semiconductor technology. The ability to operate at lower voltages without sacrificing performance could lead to more energy-efficient processors, extending battery life in portable devices and reducing the carbon footprint of data centres. For AI applications, which are computationally intensive and power-hungry, such transistors could enable more efficient hardware implementation, accelerating progress in machine learning and other AI technologies.
